t337p6 www.vishay.com vishay semiconductors rev. 1.2, 11-may-15 1 document number: 84259 for technical questions, contact: optochipsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 silicon pin photodiode description t337p6 is pin photodiode chip with 0.23 mm 2 sensitive area detecting visible and near infrared radiation. anode and cathode are the bond pads on top. features ? package type: chip ? package form: single chip ? dimensions (l x w x h in mm): 0.67 x 0.67 x 0.28 ? radiant sensitive area (in mm 2 ): 0.23 ? peak sensitivity wavelength: 970 nm ? high photo sensitivity ? suitable for visible light and near infrared radiation ? fast response times ? angle of half sensitivity: ? = 60 ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 applications ? high speed photo detector general information the datasheet is based on vishay optoel ectronics sample testing under certain predetermined and assumed conditions, and is provided for illustration purpose only. customers are encouraged to perform testing in actual proposed packaged and used conditions. vishay optoelectronics die products are tested us ing vishay optoelectronics base d quality assurance procedures and are manufactured using vishay optoelectronics established pr ocesses. estimates such as th ose described and set forth in this datasheet for semicond uctor die will vary de pending on a number of packaging, hand ling, use, and other factors. therefore sold die may not perform on an equivale nt basis to standard package products. note ? test conditions see table basic characteristics note ? moq: minimum order quantity product summary component i ra (a) ? (deg) 0.5 (nm) t337p6 2.3 60 610 to 1080 ordering information ordering code packaging remarks package form T337P6-SD-F wafer sawn on foil wi th disco frame moq: 150 000 pcs chip absolute maximum ratings (t amb = 25 c, unless otherwise specified) parameter test condition symbol value unit reverse voltage v r 60 v junction temperature t j 100 c operating temperature range t amb -40 to +100 c storage temperature range t stg1 -40 to +100 c storage temperature range on foil t stg2 -40 to +50 c
t337p6 www.vishay.com vishay semiconductors rev. 1.2, 11-may-15 2 document number: 84259 for technical questions, contact: optochipsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes ? the measurements are based on samples which ar e mounted on to18-header without epoxy coating basic characteristics (t amb = 25 c, unless otherwise specified) fig. 1 - diode capacitance vs. reverse voltage fig. 2 - relative spectral sensitivity vs. wavelength without epoxy coating basic characteristics (t amb = 25 c, unless otherwise specified) parameter test condition symbol min. typ. max. unit breakdown voltage i r = 100 a, e = 0 v (br) 60 v reverse dark current v r = 10 v, e = 0 i ro < 1 3 na diode capacitance v r = 0 v, f = 1 mhz, e = 0 c d 3.3 pf v r = 3 v, f = 1 mhz, e = 0 c d 1.5 pf reverse light current e e = 1 mw/cm 2 , = 950 nm, v r = 5 v i ra 2.3 a e e = 1 mw/cm 2 , = 890 nm, v r = 5 v i ra 2.15 a angle of half sensitivity ? 60 deg wavelength of peak sensitivity p 970 nm range of spectral bandwidth 0.5 610 to 1080 nm rise time v r = 10 v, r l = 1 k , = 950 nm t r 3500 ns fall time v r = 10 v, r l = 1 k , = 950 nm t f 820 ns rise time v r = 10 v, r l = 1 k , = 830 nm t r 550 ns fall time v r = 10 v, r l = 1 k , = 830 nm t f 100 ns 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.1 1 10 100 c p - capacitance (pf) v r - rever s e voltage (v) f = 1 mhz, e = 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 400 500 600 700 800 900 1000 1100 s ( ) rel - relative s pectral s en s itivity - wavelength (nm)
t337p6 www.vishay.com vishay semiconductors rev. 1.2, 11-may-15 3 document number: 84259 for technical questions, contact: optochipsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dimensions in millimeters mechanical dimensions parameter symbol min. typ. max. unit length of chip edge (x-direction) l x 0.67 mm length of chip ed ge (y-direction) l y 0.67 mm sensitive area a s 0.23 mm 2 wafer diameter d 150 mm die height h 0.265 0.28 0.295 mm bond pad anode ? 0.08 mm bond pad cathode ? 0.08 mm a b a c 0 . 1 5 0 . 6 0 . 6 7 * ( ) 0.07 0.335 0.67 *( ) 0 . 5 0.5 orientation of wafer flat technical drawing s according to din s pecification. opt. active area: 0.23 mm2 a: anode c: cathode bonding area: a: ? 80 m c: ? 80 m bonding re s tricted to thi s area in order to avoid damage of adjacent s tructure s thickne ss : 280 m 15 m *only for information: dimen s ion of s awn die under con s ideration of 30 m s aw kerf drawing-no.: 9.000-5123.01-4 i ss ue: 1; 08.08.2013 a ( 200 : 1 ) b ( 200 : 1 ) c a ? 0.08 (bonding area) ? 0.08 (bonding area) ? 0.096 (metallization) ? 0.096 (metallization)
t337p6 www.vishay.com vishay semiconductors rev. 1.2, 11-may-15 4 document number: 84259 for technical questions, contact: optochipsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note ? all chips are checked in accordance with the vishay semiconductor, specification of visual inspection fvov6870. the visual inspection shall be made in accordance with the specification of visual inspection as referenced. the visual inspe ction of chip backside is performed wi th stereo microscope with incident light and 40x to 80x magnification. the quality inspection (final visual inspection) is performed by production. an addition al visual inspection step as special re lease procedure by qm is not installed. handling and storage conditions ? the hermetically sealed shipment lots shall be opened in temperature and moistu re controlled cleanroom environment only. it is mandatory to follow the rules for disposition of ma terial that can be hazardous for humans and environment. ? product must be handled only at esd safe workstations. standard esd precaution s and safe work environments are as defined in mil-hdbk-263. ? singulated die are not to be handled with tweezers. a vacuum wand with non metallic esd pro tected tip shou ld be used. packing chips are fixed on adhesive foil. upon re quest the foils can be mounted on plastic frame or disco frame. for shipment, the wafers are arranged to stacks and hermeti cally sealed in plastic bags to ensure protection against environmental influence (humidity and contamination). use for recycling reliable operator s only. we can help getting in touch with your nearest sales office. by agreement we will ta ke back packing material, if it is sorted. you will have to bear the costs of transport. we will invoice you for any costs incurre d for packing material that is returned unsorted or which we are not obliged to accept. additional information frontside metallization, anode, cathode alsi backside electrically isolated dicing sawing die bonding technology epoxy bonding
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